Hardware Implementation and performance evaluation of Viterbi Decoder using Parallel decoding approach over Xilinx Virtex-6 FPGA

The wide spread use of computers and communication devices in every aspect of life demands the data transmission to be reliable as well as secure. Different design procedures and algorithms are being designed to overcome the security and reliability issues related to transmission of electronic information. Convolutional encoding with Viterbi algorithm is one of the most powerful forward error correcting schemes. It has been widely used in many of the communication areas to improve the limitation of channel capacity and power consumption of a system. This paper presents the implementation of a soft decision Viterbi decoder with code rate 1/2 for variable constraint length on Virtex-6 FPGA. Viterbi algorithm with parallel architecture has been implemented here for the purpose of achieving high decoding speed, low power consumption and for less device resource utilization. The parallel architecture implementation is then simulated through ModelSim 10.1 with 50 MHz clock rate, through which the encoded blocks are decoded in turn. Similarly, simulation result also indicates that traceback operation is started after calculating all survivor paths and thus the decoded output sequence is then presented in reverse order to that of the input information sequence KeywordsViterbi Decoder, Parallel Viterbi Decoding, Xilinx Virtex-6 FPGA, RTL Design, ModelSim